1. Field of the Invention
The present invention is in the field of semiconductor packaging.
2. Description of the Related Art
There are trends in semiconductor packaging towards packages that are highly functional, yet increasingly smaller in size so as to provide higher density in mounting. In keeping with these trends, semiconductor package 100 of FIG. 1 includes a semiconductor chip 2 which has a plurality of input-output pads 2a on a top, active surface 2b thereof. An opposite bottom, inactive surface 2c of chip 2 is bonded to a metal chip mounting substrate 4 by an adhesive 14.
Chip mounting substrate 4 has a top first side 4b bonded to chip 2 by adhesive 14, and an opposite second side 4c. Second side 4c includes an exposed bottom central surface 4d. Second side 4c of chip mounting substrate 4 has been partially etched around central surface 4d so as to form a recessed horizontal surface 4a that fully surrounds and is vertically recessed from central surface 4c. 
A plurality of horizontal metal leads 6 are arranged radially adjacent to and in the horizontal plane of chip mounting substrate 4. Leads 6 extend horizontally from an inner end 6b that faces chip mounting substrate 4 to an opposite outer end 6c. Each lead includes an upper first side 6d and an opposite lower second side 6e. Lower second side 6e includes an exposed surface portion, denoted as land 6f, that functions as an input/output terminal of package 100. Between inner end 6b and land 6f, lower second side 6e of each lead 6 includes a horizontal surface 6a that is vertically recessed from land 6f. Recessed surface 6a is formed by partially etching vertically through leads 6 from second side 6e. 
Input-output pads 2a of semiconductor chip 2 and upper side 6d of leads 6a are electrically connected to each other by conductive wires 8.
Semiconductor chip 2, conductive wires 8, chip mounting substrate 4, and leads 6 are covered by an encapsulant material that forms a package body 10. Recessed horizontal surface 4a of chip mounting substrate 4 and recessed horizontal surface 6a of leads 6 are covered by encapsulant material of package body 10. Central surface 4a of chip mounting substrate 4 and land 6f of each lead 6 are exposed at a lower horizontal surface 10a of package body 10. Package 100 is mounted by fusing lands 6f, and possibly central surface 4c, to a mother board.
Semiconductor package 100 has several drawbacks, including a relatively large mounting height, due in part to the need to cover the apex of wires 8 with the encapsulant material. In addition, package 100 has a relatively large footprint, because a predetermined lateral space between the semiconductor chip and the leads is needed to accommodate the wire bonds.
Further, semiconductor package 100 has limited avenues for heat dissipation. The primary path of heat dissipation is through exposed central surface 4d of chip mounting substrate 4. Heat is also transferred to leads 6 through conductive wires 8, but conductive wires 8 are too small to effectively transfer the heat. Further, semiconductor chip 2 is completely covered by the encapsulant material, thereby limiting heat dissipation.
Semiconductor package 100 has a further disadvantage in that the input-output pads for the ground or power inputs of the semiconductor chip are connected to the leads by conductive wires 8. Accordingly, those leads are unavailable to transfer signals for chip 2.
Moreover, semiconductor package 100 requires a relatively large lead frame in order to accommodate the semiconductor chip's fine pitched input-output pads, thereby drastically degrading the mounting density on a mother board upon which package 100 is mounted.